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TMC2242A/TMC2242B
Digital Half-Band Interpolating/Decimating Filter
12-bit In/16-bit Out, 60 MHz Features
* TMC2242A and TMC2242B are pin-compatible with TMC2242 * User selectable interpolate gain, -6 dB or 0 dB (2242B) * 30, 40 and 60 MHz speed grades * User selectable 2:1 decimation, 1:2 interpolation, and equal-rate filter modes * Passband ripple < 0.01 dB * Stopband rejection 59.4 dB from 0.28 to 0.50 x fs * Cascading two TMC2242A or TMC2242B meets CCIR 601 low-pass filter requirement * Dedicated 12-bit 2's complement input data port and 16-bit output data port with user-selectable rounding from 9 to 16 bits * Two's complement or offset binary output format * Built-in limiter prevents overflow * Single +5 Volt power supply operation * Small 44-Lead PLCC and 44-Lead MQFP
Applications
* * * * * * * * * Low-cost video filtering Chrominance bandwidth limiter Simple, inexpensive video D/A post-filters Reduced cost and complexity for A/D anti-aliasing filters High-performance digital low-pass filters Digital waveform reconstruction post-filtering Telecommunications Direct digital synthesis Radar
Description
The TMC2242A and TMC2242B are fixed-coefficient linear-phase half-band (low-pass) digital filters. They can be used to halve or double the sampling rate of a digital signal. When used as a decimating post-filter with a double-speed oversampling A/D converter, they greatly reduce the cost and complexity of anti-aliasing filters required ahead of the A/D converter. When used as an interpolating pre-filter with a double-speed oversampling D/A converter, the TMC2242A and TMC2242B significantly reduce the design complexity and production cost of reconstruction filters used on D/A outputs. The TMC2242A and TMC2242B user selects the mode of operation (decimate, interpolate, or equal-rate) and rounding. The TMC2242A and TMC2242B accept 12-bit 2's complement data at up to 60 MHz and output saturated (overflow-protected) 2's complement or offset binary data rounded to from 9 to 16 bits. Within the speed grade I/O limit, the output sample rate may be 1/2, 1, or 2 times the input sample rate.
Block Diagram
12 SI11-0 12 12 12 55 Tap FIR Filter Round and Limit 16 16 16 SO15-0 OE
CLK DEC INT SYNC Control
Interpolate 0-1-0-1 Decimate, Equal Rate 1-1-1-1 3 TCO RND2-0
65-2242A-01
Rev. 1.2.0
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Description (continued)
The filter response is flat to within 0.01 dB from 0.00 to 0.22 x fs, with stopband attenuation greater than 59.4 dB from 0.28 x fs to the Nyquist frequency. The response is 6 dB down at 0.25 x fs. Symmetric-coefficient filters such as the TMC2242A and TMC2242B have linear phase response. Full compliance with the CCIR-601 standard of 12 dB attenuation at 0.25 x fs is achieved by cascading two parts. The TMC2242A and TMC2242B are fabricated on an advanced submicron CMOS process. They are available in a 44-lead J-lead PLCC package. Performance is guaranteed from 0C to 70C. To perform decimation, the chip sets the output register clock rate to half of the input rate. One output is then obtained for every two inputs. For interpolation, the user should bring SYNC HIGH for at least one clock cycle, returning it LOW with the first desired input data value. When interpolating, the chip will then continue to accept a new data input on each alternate rising edge of the clock. When decimating, the chip will present one output value for every two clock cycles. The user may leave SYNC LOW or toggle it once per rising clock edge, with equivalent performance. The output data format is two's complement if TCO is HIGH, inverted offset binary if LOW. The user can tailor the output data word width to his/her system requirements using the Rounding control. As shown in Table 4, the output is half-LSB rounded to the resolution selected by the value of RND2-0. The asynchronous three-state output enable control simplifies connection to a data bus with other drivers.
Functional Description
The TMC2242A and TMC2242B implement a fixed-coefficient linear-phase Finite Impulse Response (FIR) filter of 55 effective taps, with special rate-matching input and output structures to facilitate 2:1 decimation and 1:2 interpolation. The faster of either the input or output registers will operate at the guaranteed maximum clock rate (speed grade). The total internal pipeline latency from the input of an impulse to the corresponding output peak (digital group delay) is 34 cycles; the 55-value output response begins after 7 clock cycles and ends after 61 cycles. To perform interpolation, the chip slows the effective input register clock rate to half the output rate. It internally inserts zeroes between the incoming data samples to "pad" the input data rate to match the output rate.
Table 1. Operating Modes
DEC 0 0 1 1 INT 0 1 0 1 TMC2242A Equal Rate Decimate Equal Rate TMC2242B Interpolate (0 dB) Decimate Equal Rate
Interpolate (-6 dB) Interpolate (-6 dB)1
Note: 1. With 15-bit overflow protection. All other modes on both parts limit to 16 bits.
Pin Assignments
SO13 SO14 SO15 OE TCO DEC INT SYNC CLK GND SI11 SO13 SO14 SO15 OE TCO DEC INT SYNC CLK GND SI11
44 43 42 41 40 39 38 37 36 35
44
43
42
41
40
6
5
4
3
2
1
18
19
20
21
22
23
24
25
26
27
28
SO12 SO11 SO10 SO9 SO8 GND VDD SO7 SO6 SO5 SO4
7 8 9 10 11 12 13 14 15 16 17
39 38 37 36 35 34 33 32 31 30 29
TMC2242A TMC2242B
GND VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD
12
13
14
15
16
17
18
19
20
21
SO3 SO2 SO1 SO0 RND2 RND1 RND0 SI0 SI1 SI2 GND
65-2242A-02 65-2242A-02
44 Lead PLCC
2
SO3 SO2 SO1 SO0 RND2 RND1 RND0 SI0 SI1 SI2 GND
44 Lead MQFP
22
SO12 SO11 SO10 SO9 SO8 GND VDD SO7 SO6 SO5 SO4
34
1 2 3 4 5 6 7 8 9 10 11
33 32 31 30 29 28 27 26 25 24 23
TMC2242A TMC2242B
GND VDD SI10 SI9 SI8 SI7 SI6 SI5 SI4 SI3 VDD
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number Pin Name INT PLCC 44 MQFP 38 Pin Function Description Interpolate. When INT is LOW and DEC is HIGH, the input data register runs at 1/2 the CLK rate and zeros are inserted in the data stream between valid input values, reducing gain by 6dB. The TMC2242A and TMC2242B interpolate and output results at the full CLK rate. Decimate. When DEC is LOW and INT is HIGH, the input data register runs at the full CLK rate. In this mode, the TMC2242A and TMC2242B decimate and output results at 1/2 the CLK rate. When INT = DEC, the TMC2242A is in equal rate mode. When both INT and DEC are HIGH, the TMC2242B is likewise in equal-rate mode, but when both INT and DEC are LOW, the TMC2242B interpolates with unity gain. In equal-rate mode, the input and output sample rates equal the chip clock rate. SYNC 43 37 Synchronization. Incoming data are synchronized by holding SYNC HIGH on CLK N-1 and LOW on CLK N when the first input data word is present on SI11-0. If DEC = INT=1 (equal rate mode), SYNC is inactive. SYNC may be held LOW until resynchronization is desired, or it may be toggled at 1/2 the CLK rate. Clock. The TMC2242A and TMC2242B operate from a single master clock. All internal registers, except the output register in decimation mode, are strobed on the rising edge of CLK. All timing parameters are referenced to the rising edge of CLK. Input Data Port. A 12-bit 2's-complement input word is registered by the rising edge of CLK. In Interpolate Mode, SI11-0 is registered on every other CLK (synchronized by SYNC). SI11 is the MSB. Output Data Port. A 16-bit 2's-complement output result is available after the rising edge of CLK. In Decimate Mode, SO15-0 is registered on every other CLK (synchronized by SYNC). SO15-0 is rounded according to the state of RND2-0. SO15 is the MSB. The limiter circuitry ensures that for internal overflow, a valid full-scale output (7FFF or 8000) will be generated. With the TMC2242B in interpolate mode with -6dB gain, limits are 3FFF and C000 (TCO=1). Output Controls OE TCO RND2-0 Power VDD GND 13,29, 38 12,28, 39,41 7, 23, 32 6, 22, 33, 35 Supply Voltage. +5 Volt power inputs. These should come from the same power source and be decoupled to GND. Ground. Ground inputs should be connected to the system digital ground plane. 3 2 22-24 41 40 16-18 Output Enable. When LOW, SO15-0 are enabled. When HIGH, SO15-0 are in a high-impedance state. OE is asynchronous with respect to CLK. Output Format. When TCO is HIGH, output data are in signed 2's-complement format. When LOW, the output is inverted offset binary. Rounding Select. These inputs set the position of the effective LSB of the output result. Outputs below the rounding bit are zeroed (Table 4). Timing Controls
DEC
1
39
CLK
42
36
Data Inputs SI11-0 40, 37-30, 27-25 4-11, 14-21 34, 31-24, 21-19 42-44, 1-5, 8-15
Data Outputs SO15-0
3
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Absolute Maximum Ratings
(beyond which the device may be damaged)1 Parameter Supply Voltage Input Voltage Output Applied Voltage2 Single output in HIGH state to ground -20 10 seconds -65 Externally Forced Current3,4 Short Circuit Duration Operating Temperature (Case) Junction Temperature Lead Soldering Temperature Storage Temperature Conditions Min -0.5 -0.5 -0.5 -3.0 Max 7.0 VDD + 0.5 VDD + 0.5 +6.0 1 110 140 300 150 Units V V V mA sec C C C C
Notes: 1. Functional operation under any of these conditions is NOT implied. Performance and reliability are guaranteed only if Operating Conditions are not exceeded. 2. Applied voltage must be current limited to specified range. 3. Forcing voltage must be limited to specified range. 4. Current is specified as conventional current flowing into the device.
Operating Conditions
Parameter VDD fCLK Power Supply Voltage Clock frequency TMC2242A, B TMC2242A-1,B-1 TMC2242A-2,B-2 tPWH tPWL tS tH VIH VIL IOH IOL TA CLK pulse width, HIGH CLK pulse width, LOW Input Data Set-up Time Input Data Hold Time Input Voltage, Logic HIGH Input Voltage, Logic LOW Output Current, Logic HIGH Output Current, Logic LOW Ambient Temperature, Still Air 0 6 6 6 1 2.0 0.8 -2.0 4.0 70 Conditions Min 4.75 Nom 5.0 Max 5.25 30 40 60 Units V MHz MHz MHz ns ns ns ns V V mA mA C
4
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Electrical Characteristics
Parameter IDD Total Power Supply Current Conditions VDD = Max, CLOAD=25pF, fCLK=Max TMC2242A,B TMC2242A-1,B-1 TMC2242A-2,B-2 IDDU Power Supply Current, Unloaded VDD = Max, OE = HIGH, fCLK=Max TMC2242A,B TMC2242A-1,B-1 TMC2242A-2,B-2 IDDQ CPIN IIH IIL IOZH IOZL IOS VOH VOL Power Supply Current, Quiescent I/O Pin Capacitance Input Current, HIGH Input Current, LOW Leakage Current, HIGH Leakage Current, LOW Short-Circuit Current Output Voltage, HIGH Output Voltage, LOW VDD = Max, VIN = VDD VDD = Max, VIN = 0 V OE = HIGH, VOUT = VDD OE = HIGH, VOUT = 0 V VDD = Max, Output = HIGH, one pin to ground, one second duration max. SO15-0, IOH = Max SO15-0, IOL = Max -20 2.4 0.4 VDD = Max, CLK = LOW 5 10 10 10 10 -80 120 155 230 5 mA mA mA mA pF mA mA mA mA mA V V 150 195 290 mA mA mA Min Typ Max Units
Switching Characteristics
Parameter tDO tHO tENA tDIS Output Delay Time Output Hold Time Output Enable Time Output Disable Time Conditions CLOAD = 25 pF CLOAD = 25 pF CLOAD = 0 pF CLOAD = 0 pF 2.5 12 12 Min Typ Max 15 Units ns ns ns ns
5
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Table 2. Impulse Response
Hex FFF2 0000 0017 0000 FFDB 0000 0039 0000 FFA8 0000 007D 0000 FF51 0000 00F3 0000 FEB5 0000 01CA 0000 FD79 0000 03CD 0000 F95E 0000 145B 2010 Decimal Equivalent -0.000875473 0.0 0.001390457 0.0 -0.002265930 0.0 0.003501892 0.0 -0.006366836 0.0 0.007621765 0.0 -0.01071167 0.0 0.01483154 0.0 -0.02018738 0.0 0.02796364 0.0 -0.03949928 0.0 0.05937767 0.0 -0.1036148 0.0 0.3180542 0.5009766 center start & end
Table 3. Step Response
INT=1 INT=1 INT=0 INT=1 DEC=1 DEC=1 DEC=1 DEC=0 Input TCO=0 TCO=1 TCO=1 TCO=1
400 400 ... 400 400 000 ... 000 000 000 000 000 ... 000
xx xx ... 3FE7 3FE7 3FE7 ... 3B90 3B90 4FEB 6FFB 8456 ... 7FFF
xx xx ... 4018 4018 4018 ... 446F 446F 3014 1004 FBA9 ... 0000
xx xx ... 2008 2010 2008 ... 245F 2010 1004 0000 FBA9 ... 0000
xx xx ... 4018 4018 4018 ... 446F 446F 1004 1004 FBA9 ... 0000 Min Ringing Steady State
DC Gain
Max Ringing
Table 4a. Input Data Format
-20 2-1 2-2 ... 2-10 2-11
Input = 0, 0, 0, ..., 0, 400h, 0, ..., 0, 0, 0 INT = DEC = TCO = 1
6
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Table 4b. Output Data Formats and Bit Weighting for TCO = 1
Interpolation Mode (TMC2242A and TMC2242B when INT = 0 and DEC = 1) -21 20 2-1 ... 26 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14
Decimation, Equal Rate Modes (and TMC2242B in unity gain interpolate mode with INT = DEC = 0) -20 2-1 2-2 ... 2-7 2-8 2-9 2-10 2-11 2-12 2-13 2-14 2-15
Rounded LSBs as a function of RND2-0 RND2-0 SO15 SO15 SO15 SO15 SO15 SO15 SO15 SO15 SO14 SO14 SO14 SO14 SO14 SO14 SO14 SO14 SO13 SO13 SO13 SO13 SO13 SO13 SO13 SO13 ... ... ... ... ... ... ... ... SO8 SO8 SO8 SO8 SO8 SO8 SO8 SO8 SO7 SO7 SO7 SO7 SO7 SO7 SO7 SO7r SO6 SO6 SO6 SO6 SO6 SO6 SO6r 0 SO5 SO5 SO5 SO5 SO5 SO5r 0 0 SO4 SO4 SO4 SO4 SO4r 0 0 0 SO3 SO3 SO3 SO3r 0 0 0 0 SO2 SO2 SO2r 0 0 0 0 0 SO1 SO1r 0 0 0 0 0 0 SO0r 0 0 0 0 0 0 0 000 001 010 011 100 101 110 111
Notes: 1. A leading minus sign denotes the two's complement sign bit. 2. When TCO=0, the most significant bit of the output is positive instead of negative. 3. In all operating modes except INT = 0 and DEC = 1, the gain is approximately unity. When INT = 0 and DEC = 1, the output gain is -6 dB. 4. The "r" indicates that the trailing significant output bit has been rounded to the nearest 1/2 LSB. (Internally, the chip adds 1 to the next lower bit, to allow the user to obtain a properly rounded output)
Table 5. TMC2242A Steady-State Output Values and Limiter Triggers (L) versus Input Data
INT = 1 or DEC = 0 Input 7FF 400 001 000 FFF C00 801 TCO = 0 0000 (L) 3FE7 7FEF 7FFF 800F C017 FFFF (L) TCO = 1 7FFF (L) 4018 0010 0000 FFF0 BFE8 8000 (L) INT = 0 and DEC = 1 TCO = 0 3FF7 / 3FE7 5FF7 / 5FEF 7FF7 7FFF 8007 A007 / A00F C007 / C017 TCO = 1 4008 / 4018 2008 / 2010 0008 0000 FFF8 DFF8 / DFF0 BFF8 / BFE8 Interpretation + full-scale +1/2 scale +1 LSB Zero -1 LSB -1/2 scale - full-scale
7
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Table 6. TMC2242B Steady-State Output Values and Limiter Triggers (L) versus Input Data
Interpolation Modes INT = 0 and DEC = 0 Input 7FF 400 001 000 FFF C00 801 TCO = 0 0000 (L) 3FEF / 3FDF 7FEF 7FFF 800F C00F / C01F FFFF TCO = 1 7FFF (L) 4010 / 4020 0010 0000 FFF0 BFF0 / BFE0 8000 (L) INT = 0 and DEC = 1 TCO = 0 4000 (L) 5FF7 / 5FEF 7FF7 7FFF 8007 A007 / A00F BFFF TCO = 1 3FFF (L) 2008 / 2010 0008 0000 FFF8 DFF8 / DFF0 C000 (L) Interpretation + full-scale +1/2 scale +1 LSB Zero -1 LSB -1/2 scale - full-scale
Decimation and Equal-Rate Modes INT = 1 Input 7FF 400 001 000 FFF C00 801 TCO = 0 0000 (L) 3FE7 7FEF 7FFF 800F C017 FFFF (L) TCO = 1 7FFF (L) 4018 0010 0000 FFF0 BFE8 8000 (L) Interpretation + full-scale +1/2 scale +1 LSB Zero -1 LSB -1/2 scale - full-scale
Performance Curves
0 -10 -20 -30 Atten (dB) -40 -50 -60
65-2242A-03
-70 -80 -90 0.00 0.10 0.20 0.30 Normalized Frequency 0.40
0.50
Figure 1. Frequency Response
8
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Performance Curves (continued)
0.10 0.08 0.06 0.04 Atten (dB) 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10 0.00 0.10 Normalized Frequency 0.20
65-32242A-04
0.30
Figure 2. Passband Ripple Response
110 100 90 80 %/Full Scale 70 60 50 40 30 20 10 0 -10 0 10 20 30 Sample 40 50 60
65-2242A-05
Figure 3. Step Response
Equivalent Circuits
VDD VDD
p Digital Input
p Digital Output n
n
GND
65-2242A-09
65-2242A-10
GND
Figure 7. Equivalent Digital Input Circuit
Figure 8. Equivalent Digital Output Circuit
9
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Timing Diagrams
1/fC CLK tS SI11-0 34 35 tH 36 37 38 tPWH tPWL
SYNC tHO SO15-0 OE is LOW. 1 2 tDO 3 4
65-2242A-06
Note: Values at SO15-0 are impulse response centers (peaks) corresponding to same-numbered inputs. Figure 4. Equal Rate Mode
1/fC CLK 34 tS SI11-0 34 35 35 tH 36 37 36
tPWH 37
tPWL 38
38
SYNC tHO SO15-0 OE is LOW. 1 3
65-2242A-07
Figure 5. Decimate Mode
1/fC CLK 34 tS SI11-0 35 35 tH 37 36
tPWH 37
tPWL 38
SYNC tHO SO15-0 OE is LOW. 1 2 tDO 3 4
65-2242A-08
Figure 6. Interpolate Mode
10
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Timing Diagrams (continued)
tENA OE Three-State Outputs 0.5V High Impedance tDIS 0.5V 2.0V 0.8V
65-2242A-11
Figure 9. Threshold Levels for Three State Measurements
Applications Discussion
The TMC2242A and TMC2242B are well-suited for filtering digitized composite NTSC or PAL video. In Figure 10, the TMC1175A 8-bit video A/D converter outputs, D7-0, are connected to the TMC2242B inputs, SI11-4, respectively (grounding SI3-0). The RND2-0 controls are set to 111 for a 9-bit rounded decimated output on SO15-7. In Figure 11, the TMC2242B drives a fast D/A converter to reconstruct analog composite video. The TMC3003 10-bit digital-to-analog converter inputs, D9-0 are connected to the TMC2242B outputs SO15-6, respectively. The TMC2242B RND2-0 controls are set to 110 for rounded 10-bit interpolation operation.
TTL Clock 27.000 MHz (D1) 28.636 MHz (NTSC D2) D7 SI11
2 uH Composite Video 75 Ohm 300 pF
2 uH 510 pF 300 pF VIN 75 Ohm
TMC1175A 8-bit A/D AGND
TMC2242B SO15 SO14-7
MSB
65-2242A-12
SI10-4 7 D6-0 DEC=0 TCO=INT=1 27.000 MHz (D1) 28.636 MHz (NTSC D2)
8
9
13.500 MHz (D1) 14.318 MHz (NTSC D2)
Figure 10. Decimating Oversampled Video With a Low Cost 8-bit A/D
TTL Clock 27.000 MHz (D1) 28.636 MHz (NTSC D2) MSB SI11 12 11 LSB TMC2242B SO15 SO14-6 9 D9 TMC3003 10-bit D/A D8-0
2 uH IOUT 75 Ohm 510 pF 300 pF
2 uH 300 pF Composite Video 75 Ohm
SI10-0
TCO=1 INT=DEC=0 13.500 MHz (D1) 14.318 MHz (NTSC D2) 27.000 MHz (D1) 28.636 MHz (NTSC D2)
AGND
65-2242A-13
Note: Data buses are unsigned binarys; TMC2242 input is two's complement. Figure 11. Interpolating Digital Video Signals before Reconstruction
11
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Notes:
12
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Notes:
13
PRODUCT SPECIFICATION
TMC2242A/TMC2242B
Mechanical Dimensions - 44-Pin PLCC Package
Symbol A A1 A2 B B1 D/E D1/E1 D3/E3 e J ND/NE N ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982 2. Corner and edge chamfer (J) = 45 3. Dimension D1 and E1 do not include mold protrusion. Allowable protrusion is .101" (.25mm)
.165 .180 .090 .120 .020 -- .013 .021 .026 .032 .685 .695 .650 .656 .500 BSC .050 BSC .042 .056 11 44 -- .004
4.19 4.57 2.29 3.05 .51 -- .33 .53 .66 .81 17.40 17.65 16.51 16.66 12.7 BSC 1.27 BSC 1.07 1.42 11 44 -- 0.10
3
2
E E1 J
D
D1
D3/E3 B1 e J
A A1 A2 B -C- LEAD COPLANARITY
ccc C
14
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Mechanical Dimensions - 44-Lead MQFP Package
Symbol A A1 A2 B C D/E D1/E1 e L N ND a ccc Inches Min. Max. Millimeters Min. Max. Notes: Notes 1. All dimensions and tolerances conform to ANSI Y14.5M-1982. 2. Dimensions "D1" and "E1" do not include mold protrusion. 3. Pin 1 identifier is optional. 4. Dimension N: number of terminals. 7 5. Dimension ND: Number of terminals per package edge. 6. "L" is the length of terminal for soldering to a substrate. 7. "B" includes lead finish thickness. 2 6 4 5
.077 .093 .000 .010 .077 .083 .012 .018 .005 .009 .510 .530 .390 .398 .032 BSC .026 .037 44 11 0 7 -- .004
1.95 2.35 .00 .25 1.95 2.11 .30 .46 .13 .23 12.95 13.45 9.90 10.10 .81 BSC .66 .94 44 11 0 7 -- 0.10
D D1
e
E E1
PIN 1 IDENTIFIER
C a
L 0.063" Ref (1.60mm)
See Lead Detail A A2 B A1 Seating Plane Base Plane -CLEAD COPLANARITY ccc C
44 Lead Metric Quad Flat Pack (MQFP) - 3.2mm Footprint
Rev 1.0
11/28/95
15
TMC2242A/TMC2242B
PRODUCT SPECIFICATION
Ordering Information
Product Number TMC2242AR2C TMC2242AR2C1 TMC2242AR2C2 TMC2242BR2C TMC2242BR2C1 TMC2242BR2C2 TMC2242AKTC TMC2242AKTC1 TMC2242AKTC2 TMC2242BKTC TMC2242BKTC1 TMC2242BKTC2 Temperature Range 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C 0C to 70C Speed Grade 30 MHz 40 MHz 60 MHz 30 MHz 40 MHz 60 MHz 30 MHz 40 MHz 60 MHz 30 MHz 40 MHz 60 MHz Screening Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Commercial Package 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 44-Lead PLCC 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP 44-Lead MQFP Package Marking 2242AR2C 2242AR2C1 2242AR2C2 2242BR2C 2242BR2C1 2242BR2C2 2242AKTC 2242AKTC1 2242AKTC2 2242BKTC 2242BKTC1 2242BKTC2
LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury of the user.
www.fairchildsemi.com 5/20/98 0.0m 001 Stock#DS7002242A O 1998 Fairchild Semiconductor Corporation
2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.

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